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19-2632; Rev 0; 10/02
4.5 Dual SPST Analog Switches in UCSP
General Description
The MAX4721/MAX4722/MAX4723 low-voltage, low onresistance (RON), dual single-pole/single throw (SPST) analog switches operate from a single +1.8V to +5.5V supply. These devices are designed for USB 1.1 and audio switching applications. The MAX4721/MAX4722/MAX4723 feature 4.5 RON (max) with 1.2 flatness and 0.3 matching between channels. These new switches feature guaranteed operation from +1.8V to +5.5V and are fully specified at 3V and 5V. These switches offer break-before-make switching (1ns) with t ON <80ns and t OFF <40ns at +2.7V. The digital logic inputs are +1.8V logic compatible with a +2.7V to +3.6V supply. These switches are packaged in a chip-scale package (UCSPTM), significantly reducing the required PC board area. The chip occupies only a 1.52mm 1.52mm area and has a 3 3 bump array with a bump pitch of 0.5mm. These switches are also available in an 8-pin MAX package. o o o o o o o o o o o o o o USB 1.1 Signal Switching <2ns Differential Skew -3dB Bandwidth: >300MHz Low 15pF On-Channel Capacitance Low RON (max) Switches 4.5 (max) (+3V Supply) 3 (max) (+5V Supply) 0.3 (max) RON Match (+3V Supply) 1.2 (max) RON Flatness (+3V Supply) <0.5nA Leakage Current at TA = +25C High Off-Isolation: -55dB (10MHz) Low Crosstalk: -80dB (10MHz) Low Distortion: 0.03% +1.8V CMOS-Logic Compatible Single-Supply Operation from +1.8V to +5.5V Rail-to-Rail(R) Signal Handling
Features
MAX4721/MAX4722/MAX4723
Applications
Battery-Operated Equipment Audio/Video-Signal Routing Low-Voltage Data-Acquisition Systems Sample-and-Hold Circuits Communications Circuits
PART MAX4721EUA MAX4721EBL-T* MAX4722EUA MAX4722EBL-T* MAX4723EUA MAX4723EBL-T*
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN/BUMPPACKAGE 8 MAX 9 UCSP-9 8 MAX 9 UCSP-9 8 MAX 9 UCSP-9 TOP MARK -- ABP -- ABQ -- ABR
Note: UCSP package requires special solder temperature profile described in the Absolute Maximum Ratings section. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. UCSP is a trademark of Maxim Integrated Products, Inc. *UCSP reliability is integrally linked to the user's assembly methods, circuit board material, and environment. See the UCSP reliability notice in the UCSP Reliability section of this data sheet for more information.
Pin Configurations/Functional Diagrams/Truth Tables
MAX4721 TOP VIEW
(BUMP SIDE DOWN) A IN2 B COM1 C NO1 V+ IN1 COM2 C NC1 V+ IN1 GND NO2 B COM1 COM2 C NO1 V+ IN1 A IN2 GND NC2 B COM1 COM2 A IN2 GND NC2 IN_ LOW HIGH NO_ OFF ON NC_ ON OFF 1 2 3 1
MAX4722
2 3 1
MAX4723
2 3
UCSP
UCSP
UCSP 1
________________________________________________________________ Maxim Integrated Products
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4.5 Dual SPST Analog Switches in UCSP MAX4721/MAX4722/MAX4723
ABSOLUTE MAXIMUM RATINGS
(All Voltages Referenced to GND, Unless Otherwise Noted.) V+, IN_...................................................................-0.3V to +6.0V COM_, NO_, NC_ (Note 1) ...........................-0.3V to (V+ + 0.3V) Continuous Current COM_, NO_, NC_ ...........................100mA Peak Current COM_, NO_, NC_ (pulsed at 1ms, 10% duty cycle)................................200mA Continuous Power Dissipation (TA = +70C) 8-Pin MAX (derate 4.5mW/C above +70C) .............362mW 9-Bump UCSP (derate 4.7mW/C above +70C).........379mW ESD Method 3015.7 .............................................................>2kV Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Bump Temperature (soldering) (Note 2) Infrared (15s) ...............................................................+220C Vapor Phase (60s) .......................................................+215C
Note 1: Signals on COM_, NO_, or NC_ exceeding V+ or GND are clamped by internal diodes. Limit forward-diode current to maximum current rating. Note 2: This device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device can be exposed to during board level solder attach and rework. This limit permits only the use of the solder profiles recommended in the industry standard specification, JEDEC 020A, paragraph 7.6, table 3 for IR/VPR and convection reflow. Preheating is required. Hand or wave soldering is not allowed.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--Single +3V Supply
(V+ = +2.7V to +3.6V, VIH = +1.4V, VIL = +0.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3.0V, TA = +25C, unless otherwise noted.) (Notes 3, 4)
PARAMETER Analog Signal Range ANALOG SWITCH +25C On-Resistance (Note 5) RON V+ = 2.7V, ICOM_ = 10mA; VNO_ or VNC_ = 1.5V V+ = 2.7V, ICOM_ = 10mA; VNO_ or VNC_ = 1.5V V+ = 2.7V, ICOM_ = 10mA; VNO_ or VNC_ = 1.0V, 1.5V, 2.0V V+ = 3.6V, VCOM_ = 0.3V, 3.3V; VNO_ or VNC_ = 3.3V, 0.3V TMIN to TMAX +25C On-Resistance Match Between Channels (Notes 5, 6) RON TMIN to TMAX +25C On-Resistance Flatness (Note 7) RFLAT(ON) TMIN to TMAX +25C NO_, NC_ Off-Leakage Current (Note 8) INO_(OFF), INC_(OFF) TMIN to TMAX +25C COM_ Off-Leakage Current (Note 8) ICOM_ (OFF), V+ = 3.6V, VCOM_ = 0.3V, 3.3V; ICOM_ (OFF) VNO_ or VNC_ = 3.3V, 0.3V V+ = 3.6V, VCOM_ = 0.3V, 3.3V; VNO_ or VNC_ = 0.3V, 3.3V, or floating VNO_, VNC_ = 1.5V; RL = 300, CL = 35pF, Figure 1 TMIN to TMAX +25C TMIN to TMAX +25C Turn-On Time tON TMIN to TMAX -0.5 -1.5 -0.5 -1.5 -1 -2 40 +0.01 +0.01 +0.01 0.6 0.1 3.0 4.5 5 0.3 0.4 1.2 1.5 +0.5 +1.5 +0.5 +1.5 +1 +2 80 100 ns nA nA nA SYMBOL VCOM_, VNO_, VNC_ CONDITIONS TA MIN 0 TYP MAX V+ UNITS V
COM_ On-Leakage Current (Note 8)
ICOM_(ON)
2
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4.5 Dual SPST Analog Switches in UCSP
ELECTRICAL CHARACTERISTICS--Single +3V Supply (continued)
(V+ = +2.7V to +3.6V, VIH = +1.4V, VIL = +0.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3.0V, TA = +25C, unless otherwise noted.) (Notes 3, 4)
PARAMETER DYNAMIC CHARACTERISTICS +25C Turn-Off Time tOFF VNO_, VNC_ = 1.5V; RL = 300, CL = 35pF, Figure 1 VNO_, VNC_ = 1.5V; RL = 300, CL = 35pF, Figure 2 RS = 39, CL = 50pF, Figure 3 VGEN = 2V, RGEN = 0, CL = 1.0nF, Figure 4 f = 10MHz; VNO_, VNC_ = 1VP-P; RL = 50, CL = 5pF, Figure 5a f = 1MHz; VNO_, VNC_ = 1VP-P; RL = 50, CL = 5pF, Figure 5a f = 10MHz; VNO_, VNC_ = 1VP-P; RL = 50, CL = 5pF, Figure 5b f = 1MHz; VNO_, VNC_ = 1VP-P; RL = 50, CL = 5pF, Figure 5b Signal = 0dBm, CL = 5pF, RL = 50, Figure 5a RL = 600 +25C +25C +25C +25C TMIN to TMAX TMIN to TMAX V+ = +3.6V, VIN_ = 0 or 5.5V TMIN to TMAX TMIN to TMAX V+ = 5.5V, VIN_ = 0V or V+ TMIN to TMAX -0.1 TMIN to TMAX +25C Break-Before-Make Time Delay (MAX4723 Only) (Note 8) Skew (Note 8) Charge Injection tBBM TMIN to TMAX TMIN to TMAX +25C 1 0.15 5 -55 +25C -80 -80 +25C -110 >300 0.03 9 15 MHz % pF pF dB dB 0.2 8 ns 20 40 50 ns SYMBOL CONDITIONS TA MIN TYP MAX UNITS
MAX4721/MAX4722/MAX4723
tSKEW Q
ns pC
Off-Isolation (Note 9)
VISO
Crosstalk (Note 10)
VCT
On-Channel -3dB Bandwidth Total Harmonic Distortion NO_, NC_ Off-Capacitance Switch On-Capacitance DIGITAL I/O Input Logic High Voltage Input Logic Low Voltage Input Leakage Current SUPPLY Supply Voltage Range Positive Supply Current
BW THD
CNO_(OFF) f = 1MHz, Figure 6 CNC_(OFF) C(ON) f = 1MHz, Figure 6
VIH VIL IIN
1.4 0.5 +0.1
V V A
V+ I+
1.8
5.5 1
V A
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3
4.5 Dual SPST Analog Switches in UCSP MAX4721/MAX4722/MAX4723
ELECTRICAL CHARACTERISTICS--Single +5V Supply
(V+ = +4.2V to +5.5V, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5.0V, TA = +25C, unless otherwise noted.) (Notes 3, 4)
PARAMETER Analog Signal Range ANALOG SWITCH +25C On-Resistance (Note 5) RON V+ = 4.2V, ICOM_ = 10mA; VNO_ or VNC_ = 3.5V V+ = 4.2V, ICOM_ = 10mA; VNO_ or VNC_ = 3.5V V+ = 4.2V, ICOM_ = 10mA; VNO_ or VNC_ = 1.0V, 2.0V, 3.5V V+ = 5.5V, VCOM_ = 1.0V, 4.5V; VNO_ or VNC_ = 4.5V, 1.0V V+ = 5.5V, VCOM_ = 1V, 4.5V; VNO_ or VNC_ = 4.5V, 1V V+ = 5.5V, VCOM_ = 1.0V, 4.5V; VNO_ or VNC_ = 1.0V, 4.5V, or floating TMIN to TMAX +25C On-Resistance Match Between Channels (Notes 5, 6) RON TMIN to TMAX +25C On-Resistance Flatness (Note 7) RFLAT(ON) TMIN to TMAX +25C NO_, NC_ Off-Leakage Current (Note 8) INO_(OFF), INC_(OFF) TMIN to TMAX +25C COM _ Off-Leakage Current (Note 8) ICOM_(OFF) TMIN to TMAX +25C TMIN to TMAX +25C Turn-On Time tON VNO_, VNC_ = 3.0V; RL = 300, CL = 35pF, Figure 1 VNO_, VNC_ = 3.0V; RL = 300, CL = 35pF, Figure 1 VNO_, VNC_ = 3.0V; RL = 300, CL = 35pF, Figure 2 RS = 39, CL = 50pF, Figure 3 TMIN to TMAX +25C Turn-Off Time tOFF TMIN to TMAX +25C Break-Before-Make Time Delay (MAX4723 Only) (Note 8) Skew (Note 8) DIGITAL I/O Input Logic High Voltage Input Logic Low Voltage VIH VIL TMIN to TMAX TMIN to TMAX 2.0 0.8 V V tBBM TMIN to TMAX TMIN to TMAX 1 1.5 2 8 ns 20 -0.5 -1.5 -0.5 -1.5 -1 -2 +0.01 +0.01 +0.01 0.4 0.1 1.7 3.0 3.5 0.3 0.4 1.2 1.5 +0.5 +1.5 +0.5 +1.5 +1 +2 nA nA nA SYMBOL VCOM_, VNO_, VNC_ CONDITIONS TA TMIN to TMAX MIN 0 TYP MAX V+ UNITS V
COM_ On-Leakage Current (Note 8) DYNAMIC CHARACTERISTICS
ICOM_(ON)
30
80 90 40 50 ns ns
tSKEW
ns
4
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4.5 Dual SPST Analog Switches in UCSP
ELECTRICAL CHARACTERISTICS--Single +5V Supply (continued)
(V+ = +4.2V to +5.5V, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5.0V, TA = +25C, unless otherwise noted.) (Notes 3, 4)
PARAMETER Input Leakage Current POWER SUPPLY Power-Supply Range Positive Supply Current V+ I+ V+ = 5.5V, VIN_ = 0V or V+ TMIN to TMAX TMIN to TMAX 1.8 5.5 1 V A SYMBOL IIN CONDITIONS V+ = 5.5V, VIN_ = 0V or V+ TA TMIN to TMAX MIN -0.1 TYP MAX +0.1 UNITS A
MAX4721/MAX4722/MAX4723
UCSP parts are 100% tested at +25C only, and guaranteed by design over the specified temperature range. MAX parts are 100% tested at TMAX and guaranteed by design over the specified temperature range. Note 4: The algebraic convention used in this data sheet is where the most negative value is a minimum and the most positive value is a maximum. Note 5: Guaranteed by design for UCSP parts. Note 6: RON = RON(MAX) - RON(MIN). Note 7: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges. Note 8: Guaranteed by design. Note 9: Off-Isolation = 20log10 (VCOM / VNO), VCOM = output, VNO = input to off switch. Note 10: Between any two switches. Note 3:
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
ON-RESISTANCE vs. VCOM
MAX4721/22/23 toc01
ON-RESISTANCE vs. VCOM
MAX4721/22/23 toc02
ON-RESISTANCE vs. VCOM
V+ = 5V
MAX4721/22/23 toc03
10 V+ = 1.8V
6 V+ = 3V 5
5
8
4
RON ()
RON ()
4
V+ = 3V
V+ = 4.2V
3
TA = +25C
RON ()
6
V+ = 2.5V
4
TA = +85C
3
TA = +85C
2
2 V+ = 5V 0 1 2 3 4 5
2 TA = -40C 1 0 0.5 1.0 1.5 VCOM (V) 2.0 2.5 3.0
1 TA = -40C 0 0 1 2 3 4 5 VCOM (V) TA = +25C
0 VCOM (V)
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5
4.5 Dual SPST Analog Switches in UCSP MAX4721/MAX4722/MAX4723
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
LEAKAGE CURRENT vs. TEMPERATURE
MAX4721/22/23 toc04a
LEAKAGE CURRENT vs. TEMPERATURE
V+ = 5V 800 LEAKAGE CURRENT (pA)
MAX4721/22/23 toc04b
CHARGE INJECTION vs. VCOM
MAX4721/22/23 toc05
500 V+ = 3V 400 LEAKAGE CURRENT (pA)
1000
50
40 CHARGE INJECTION (pC) CL = 1nF V+ = 5V 30 CL = 1nF V+ = 3V
300
COM ON-LEAKAGE COM OFF-LEAKAGE
600 COM ON-LEAKAGE COM OFF-LEAKAGE 400
200
20
100
200
10
0 -40 -15 10 35 60 85 TEMPERATURE (C)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
0 0 1 2 3 4 5 VCOM (V)
SUPPLY CURRENT vs. TEMPERATURE
MAX4721/22/23 toc06
SUPPLY CURRENT vs. LOGIC LEVEL
MAX4721/22/23 toc07
TURN-ON/OFF TIME vs. SUPPLY VOLTAGE
MAX4721/22/23 toc08
6 5 SUPPLY CURRENT (nA) 4 V+ = 5V 3 2 1 0 -40 -15 10 35 60 V+ = 3V
100
100
80 SUPPLY CURRENT (A) V+ = 5V 60
80 tON/tOFF (ns)
60 tON 40 tOFF 20
40 V+ = 3V 20
0 85 0 1 2 3 4 5 TEMPERATURE (C) LOGIC LEVEL (V)
0 1.5 2.5 3.5 4.5 5.5 SUPPLY VOLTAGE (V)
TURN-ON/OFF TIME vs. TEMPERATURE
MAX4721/22/23 toc09
RISE/FALL-TIME DELAY vs. SUPPLY VOLTAGE
MAX4721/22/23 toc10
RISE/FALL-TIME DELAY vs. TEMPERATURE
OUTPUT RISE/FALL-TIME DELAY (ns) INPUT RISE/FALL TIME = 15ns FIGURE 3, CL = 50pF V+ = 4.2V 1.5
MAX4721/22/23 toc11
60 50 40 30 20 tOFF, V+ = 3.0V 10 0 -40 -15 10 35 60 tOFF, V+ = 5.0V tON, V+ = 3.0V
3.0 OUTPUT RISE/FALL-TIME DELAY (ps) 2.5 2.0 1.5 RISE DELAY 1.0 0.5 0 FALL DELAY INPUT RISE/FALL TIME = 15ns FIGURE 3, CL = 50pF
2.0
tON, V+ = 5.0V
tON/tOFF (ns)
1.0 RISE DELAY 0.5
FALL DELAY
0 1.5 2.5 3.5 4.5 5.5 -40 -15 10 35 60 85 SUPPLY VOLTAGE (V) TEMPERATURE (C)
85
TEMPERATURE (C)
6
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4.5 Dual SPST Analog Switches in UCSP
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
RISE TIME TO FALL TIME MISMATCH vs. SUPPLY VOLTAGE
MAX4721/22/23 toc12
MAX4721/MAX4722/MAX4723
RISE TIME TO FALL TIME MISMATCH vs. TEMPERATURE
MAX4721/22/23 toc13
SKEW vs. SUPPLY VOLTAGE
INPUT RISE/FALL TIME = 15ns FIGURE 3, CL = 50pF 300 SKEW (ps)
MAX4721/22/23 toc14
400 INPUT RISE/FALL TIME = 15ns FIGURE 3, CL = 50pF 300 MISMATCH (ps)
200 INPUT RISE/FALL TIME = 15ns FIGURE 3, CL = 50pF V+ = 4.2V 150 MISMATCH (ps)
400
200
100
200
100
50
100
0 1.5 2.5 3.5 4.5 5.5 SUPPLY VOLTAGE (V)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
0 1.5 2.5 3.5 4.5 5.5 SUPPLY VOLTAGE (V)
SKEW vs. TEMPERATURE
MAX4721/22/23 toc15
FREQUENCY RESPONSE
V+ = 3V/5V 0 -20 ON-LOSS (dB) -40 -60 -80 -100 -120 CROSSTALK OFF-ISOLATION ON-LOSS
MAX4721/22/23 toc16
200 INPUT RISE/FALL TIME = 15ns FIGURE 3, CL = 50pF V+ = 4.2V 150 SKEW (ps)
20
100
50
0 -40 -15 10 35 60 85 TEMPERATURE (C)
-140 0.0001
0.01
1
100
FREQUENCY (MHz)
V+ = 3V RL = 600
MAX4721/22/23 toc17
1
1.6 LOGIC THRESHOLD (V) VTH+ 1.2 VTH0.8
THD (%)
0.1
0.4
0 0.01 10 100 1k FREQUENCY (Hz) 10k 100k 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
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MAX4721/22/23 toc18
TOTAL HARMONIC DISTORTION vs. FREQUENCY
LOGIC THRESHOLD vs. SUPPLY VOLTAGE
2.0
7
4.5 Dual SPST Analog Switches in UCSP MAX4721/MAX4722/MAX4723
Pin Description
PIN MAX4721 UCSP A1 A2 A3 B1 B3 C1 C2 C3 -- -- MAX 3 4 5 2 6 1 8 7 -- -- MAX4722 UCSP A1 A2 -- B1 B3 -- C2 C3 C1 A3 MAX 3 4 -- 2 6 -- 8 7 1 5 MAX4723 UCSP A1 A2 -- B1 B3 C1 C2 C3 -- A3 MAX 3 4 -- 2 6 1 8 7 -- 5 IN2 GND NO2 COM1 COM2 NO1 V+ IN1 NC1 NC2 Logic-Control Digital Input Ground. Connect to digital ground. Analog-Switch Normally Open Terminal Analog-Switch Common Terminal Analog-Switch Common Terminal Analog-Switch Normally Open Terminal Positive Analog Supply Logic-Control Digital Input Analog-Switch Normally Closed Terminal Analog-Switch Normally Closed Terminal NAME FUNCTION
Detailed Description
The MAX4721/MAX4722/MAX4723 dual SPST analog switches operate from a single +1.8V to +5.5V supply. The MAX4721/MAX4722/MAX4723 offer excellent AC characteristics, <0.5nA leakage current, less than 2ms differential skew, and 15pF on-channel capacitance. All of these devices are CMOS-logic compatible with railto-rail signal handling capability. The MAX4721/MAX4722/MAX4723 are USB-compliant switches that provide 4.5 (max) on-resistance, and 15pF on-channel capacitance to maintain signal integrity. At 12Mbps (USB full-speed data rate specification) the MAX4721/MAX4722/MAX4723 introduce less than 2ns propagation delay between input and output signals and less than 0.5ns change in skew for the output signals (see Figure 3 for more details). The MAX4721 has two normally open (NO) switches, the MAX4722 has two normally closed (NC) switches, and the MAX4723 has one NO switch and one NC switch.
Applications Information
Digital Control Inputs
The MAX4721/MAX4722/MAX4723 logic inputs accept up to +5.5V regardless of supply voltage. For example, with a +3.3V supply, IN_ can be driven low to GND and high to +5.5V allowing for mixing of logic levels in a system. Driving the control logic inputs rail-to-rail minimizes power consumption. For a +3.0V supply voltage, the logic thresholds are 0.5V (low) and 1.4V (high); for a +5V supply voltage, the logic thresholds are 0.8V (low) and 2.0V (high).
Analog Signal Levels
Analog signals that range over the entire supply voltage (V+ to GND) are passed with very little change in on-resistance (see the Typical Operating Characteristics). The switches are bidirectional, so the NO_, NC_, and COM_ pins can be either inputs or outputs.
8
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4.5 Dual SPST Analog Switches in UCSP
Test Circuits/Timing Diagrams
MAX4721/ MAX4722/ MAX4723
VN_ V+ V+ COM_ RL IN_ LOGIC INPUT GND CL INCLUDES FIXTURE AND STRAY CAPACITANCE. RL RL - RON SWITCH OUTPUT 0V t ON LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE. LOGIC INPUT VOUT CL VOUT VIH 50% VIL t OFF 0.9 x V0UT 0.9 x VOUT
MAX4721/MAX4722/MAX4723
NO_ OR NC_
VOUT = VCOM
(
)
Figure 1. Switching Time
MAX4723
COM1 COM2 IN_ LOGIC INPUT GND
V+ V+ VOUT1 VOUT2 RL2 CL2 RL1
LOGIC INPUT NO_ NC_
VIH 50% VIL
VCOM1 VCOM2
CL1
SWITCH OUTPUT 1 (VOUT1) SWITCH OUTPUT 2 (VOUT2)
0.9 x V0UT1 0V
0.9 x VOUT2 0V tD tD
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 2. Break-Before-Make Interval
Power-Supply Bypassing
Power-supply bypassing improves noise margin and prevents switching noise from propagating from the V+ supply to other components. A 0.1F capacitor connected from V+ to GND is adequate for most applications.
UCSP Reliability
The chip-scale package (UCSP) represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical reliability tests. UCSP reliability is integrally linked to the user's assembly methods, circuit board material, and usage environment. The user should closely review these areas when considering use of a UCSP package. Performance through Operating Life Test and Moisture Resistance remains uncompromised as it is primarily determined by the wafer-fabrication process. Mechanical stress performance is a greater consideration for a UCSP package. UCSPs are attached through direct solder contact to the user's PC board, foregoing the inherent stress relief of a packaged product lead frame. Solder joint contact integrity must be considered. Information on Maxim's qualification plan, test data, and recommendations are detailed in the UCSP application note, which can be found on Maxim's website at www.maxim-ic.com.
9
Power-Supply Sequencing and Overvoltage Protection
Caution: Do not exceed the absolute maximum ratings because stresses beyond the listed ratings may cause permanent damage to the device.
UCSP Package Considerations
For general UCSP package information and PC layout considerations, please refer to the Maxim Application Note (Wafer-Level Chip-Scale Package).
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4.5 Dual SPST Analog Switches in UCSP MAX4721/MAX4722/MAX4723
Test Circuits/Timing Diagrams (continued)
tri 50% TxD+ Rs A B CL INPUT A90% 50% 10% tfi INPUT A 10% tskew_i
90%
tro 50%
90%
TxDRs Rs = 39 CL = 50pF
A-
BCL
OUTPUT B OUTPUT B-
10%
tskew_o 90% 50% 10% tfo
|tro - tri| DELAY DUE TO SWITCH FOR RISING INPUT AND RISING OUTPUT SIGNALS. |tfo - tfi| DELAY DUE TO SWITCH FOR FALLING INPUT AND FALLING OUTPUT SIGNALS.
|tskew_o| CHANGE IN SKEW THROUGH THE SWITCH FOR OUTPUT SIGNALS. |tskew_i| CHANGE IN SKEW THROUGH THE SWITCH FOR INPUT SIGNALS.
Figure 3. Input/Output Skew Timing Diagram
10
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4.5 Dual SPST Analog Switches in UCSP
Test Circuits/Timing Diagrams (continued)
V+
MAX4721/MAX4722/MAX4723
MAX4721/ MAX4722/ MAX4723
VOUT VOUT VOUT CL IN OFF ON OFF
V+ RGEN NC_ OR NO_ GND IN_ COM_
V GEN
VIL TO VIH
IN
OFF
ON Q = (V OUT )(C L )
OFF
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE.
Figure 4. Charge Injection
V+ C = 0.1F C = 0.1F SIGNAL GENERATOR 0dBm 50* V+ NC_ or NO_ V+
MAX4721/ MAX4722/ MAX4723
NO1 50
MAX4721/ MAX4722/ MAX4723
0V OR V+ IN_
SIGNAL GENERATOR 0dBm
V+ COM1 IN1
0V TO V+ NO2 GND
IN2 COM2
0V OR V+
ANALYZER
COM_ GND ANALYZER N.C.
*USED ONLY FOR OFF-ISOLATION TEST.
Figure 5a. On-Loss, Off-Isolation, and Crosstalk
Figure 5b. Crosstalk Test Circuit
C = 0.1F
V+
Chip Information
TRANSISTOR COUNT: 181 PROCESS: BiCMOS
MAX4721/ MAX4722/ MAX4723
IN_ 0V OR V+
V+ NC_ or NO_
CAPACITANCE METER COM_ f = 1MHz GND
Figure 6. Channel Off/On-Capacitance ______________________________________________________________________________________ 11
4.5 Dual SPST Analog Switches in UCSP MAX4721/MAX4722/MAX4723
Pin Configurations/Functional Diagrams/Truth Tables (continued)
TOP VIEW MAX4721
NO1 COM1 IN2 GND 1 2 3 4 8 7 6 5 V+ IN1 COM2 NO2 NC1 COM1 IN2 GND 1 2 3 4
MAX4722
8 7 6 5 V+ IN1 COM2 NC2 NO1 COM1 IN2 GND 1 2 3 4
MAX4723
8 7 6 5 V+ IN1 COM2 NC2
MAX
LOGIC 0 1 SWITCH OFF ON
MAX
LOGIC 0 1 SWITCH ON OFF
MAX
LOGIC SWITCH1 SWITCH2 0 OFF ON 1 ON OFF
SWITCHES SHOWN FOR LOGIC "0" INPUT
12
______________________________________________________________________________________
4.5 Dual SPST Analog Switches in UCSP
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX4721/MAX4722/MAX4723
______________________________________________________________________________________
13
4.5 Dual SPST Analog Switches in UCSP MAX4721/MAX4722/MAX4723
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
8LUMAXD.EPS
8
4X S
8
INCHES DIM A A1 A2 b c D e E H MIN 0.002 0.030 MAX 0.043 0.006 0.037
MILLIMETERS MAX MIN 0.05 0.75 1.10 0.15 0.95
y 0.500.1 0.60.1
E
H
1
0.60.1
1
D
L
S
BOTTOM VIEW
0.014 0.010 0.007 0.005 0.120 0.116 0.0256 BSC 0.120 0.116 0.198 0.188 0.026 0.016 6 0 0.0207 BSC
0.25 0.36 0.13 0.18 2.95 3.05 0.65 BSC 2.95 3.05 5.03 4.78 0.41 0.66 0 6 0.5250 BSC
TOP VIEW
A2
A1
A
e
c b L
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0036
J
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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